1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the semiconductor device.
Priority is claimed on Japanese Patent Application No. 2008-318618, filed Dec. 15, 2008, the content of which is incorporated herein by reference.
2. Description of the Related Art
In recent years, there has been increased the degree of integration of semiconductor devices such as a dynamic random access memory (DRAM) or a parameter random access memory (PRAM), due to increasing the requirements for advanced functions of the semiconductor devices.
Japanese Unexamined Patent Application, First Publications, Nos. JP-A-7-273221 and JP-T-2002-541667 address that the past semiconductor device had a problem in that the area occupied two-dimensionally by the semiconductor device decreased with the increase in degree of integration and thus the size of a region in which a transistor is formed, that is, an active region, gradually decreases. Specifically, the channel length of a planar transistor decreased with the decrease in size of the active region, thereby causing a so-called short channel effect. Accordingly, to increase the channel length and the width in a limited region, a semiconductor device was suggested in which a three-dimensional transistor such as a vertical transistor is formed instead of the past planar transistor. Specifically, a semiconductor has been suggested which has a configuration in which a silicon substrate is formed in a pillar shape and an MOS transistor having an upper diffusion layer at the uppermost, a channel region surrounded with a gate electrode at the center, and a lower diffusion layer close to the substrate is formed therein.
Japanese Unexamined Patent Application, First Publication, No. JP-A-2007-329480 discloses that in such a vertical transistor, a method of forming an embedded bit line using an ion introducing method was employed and a method of forming the embedded bit line as a silicide layer was suggested.